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| rev.2.00, sep.04.2003, page 1 of 17 M65665DSP picture-in-picture signal processing rej03f0012-0100z rev.2.00 sep.04.2003 description the M65665DSP is a pip (picture in picture) signal processing lsi, whose sub-picture input is composite signal or component signals(y/c or y/u/v) for ntsc , pal-m , pal-n. the built-in field memory (168k-bit ram) , v-chip data slicer and analog circuitries lead the high quality pip system low cost and small size. features ? internal v-chip data slicer (for sub-picture) ? vertical filter for sub-picture (y signal) ? base band com filter (2 line) ? single sub-picture (selectable picture size : 1/9 , 1/16) ? sub-picture processing specification (1/9 , 1/16 size) : quantization bits y, b-y, r-y : 7 bits horizontal sampling 229 pixels (y), 57 pixels (b-y, r-y) vertical lines 69/ 52 lines ? frame (sub-picture) on/off ? built-in analog circuits : two 8-bit a/d converters (for sub-picture signal) three 8-bit d/a converters (for y, u and v of sub-picture) auto slicer(sync sep.), sync-tip-clamp, vcxo, osd switch, etc.. ? i 2 c bus control (parallel/serial control) : pip on/off , frame on/off (programmable luma level), sub-picture size (1/9, 1/16), pip position (free position), picture freeze , y delay adjustment, chroma level, tint, black level, contrast ...etc.. application ntsc , pal-m , pal-n color tv recommended operating conditions supply voltage range --------------------- 3.2 to 3.5 v recommended supply voltage --------------------- 3.3 v
M65665DSP rev.2.00, sep.04.2003, page 2 of 17 pin configuration (top view) 123456789 111213141516 10 17 18 19 20 21 vrb vrt a vdd(adc) testen csyncs reset swmg osd_sel test5 sdata fsc bgpm sck dvss dvdd swm sclk bgps vin(adc) uin(adc) yin( adc) 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 22 23 24 25 26 avss(adc) cvbsin(adc) avdd(vcxo) bias filter x'tal(ntsc) avss(vcxo) vd hd cin(adc) v(b)out osd_gin u(g)out osd_rin y(r)out vdd(dac) agnd(dac) vz os d_bin xxxxxx M65665DSP 42 pin sdip package : 42p4b x'tal(pal-m) x'tal(pal-n) M65665DSP rev.2.00, sep.04.2003, page 3 of 17 block diagram scl sda reset vertical filter demod. & tint pip field memory y/r output main vd main hd i 2 c i/f output control & rgb matrix pip sw b.p.f. avdd agnd dvdd dgnd testen + sub picture(u) sub picture(v) sub picture (cvbs or y(y/c)) rextin gextin bexttin i 2 c bus vcxo b.gate & p.d. sub picture( c) osd_sel sub picture (y(y/u/v)) comb filter y u v 42 u/g output 39 v/b output 36 1 sub-dac dac sub-dac dac sub-dac i 2 c bus i 2 c bus i 2 c bus dac 37 41 38 35 2 14 12 11 10 13 15 9 8 7 6 5 19 21 34 40 31 23 16 25 3 4 30 29 28 27 26 32 33 22 17 18 20 24 l.p.f. sw sw a/d a/d mux sync. auto slice(analog) sync. slice(analog) sync. sep.(digital ) v-chip data sl icer timing gen. ext. c-sync analog switch demux & enco der M65665DSP rev.2.00, sep.04.2003, page 4 of 17 absolute maximum ratings (vss=0 v) limits parameter symbol min. max. unit conditions supply voltage (3.3v) vdd3 ? 0.3 4.2 v input voltage (except for 5v input) vi3 ? 0.3 vdd3+0.3 v input voltage (5v) vi5 ? 0.3 5.25 v output voltage vo ? 0.3 vdd3+0.3 v output current (*1) io ioh= ? 4 iol=4 ma operating temperature topr ? 10 70 deg. storage temperature tstg ? 50 125 deg. note : 1. output current per output terminal. but pd limits all current. 0255075100125 400 800 0 thermal derating (maximum rating) 1200 1600 2000 power dissipation pd (mw) ambient temperature ta (deg.) 70 750 1350 recommended operating conditions (ta = 25 c, unless otherwise noted) parameter symbol min. typ. max. unit conditions supply voltage vdd3 3.2 3.3 3.5 v operating frequency fopr ? 14.32 ? mhz ? h ? input voltage (cmos interface) vih vdd3 0.7 ? vdd3 v ? l ? input voltage (cmos interface) vil 0 ? vdd3 0.3 v output current (output buffer) io ? ? 2 ma output load capacitance c ol ? ? 20 pf include pin capacitance (7pf) M65665DSP rev.2.00, sep.04.2003, page 5 of 17 dc characteristics (ta = 25 deg. unless otherwise noted) (vss=0v) limits parameter symbol min. typ. max. unit conditions input voltage (3.3v cmos interface) l vil 0 ? 0.81 v vdd=2.7v h vih 2.52 ? 3.6 v vdd=3.6v input current (3.3v cmos interface) l iil3 ? 10 ? 10 a vdd=3.6v,vi=0v h iih3 ? 10 ? 10 a vdd=3.6v,vi=3.6v input voltage schmitt (5.0v cmos interface) ? vt- 0.8 ? 1.65 v vdd=3.3v + vt+ 1.4 ? 2.7 v hysteresis vh 0.3 ? 1.2 v input current (5.0v cmos interface) l iil5 ? 100 ? 10 a vdd=3.6v,vi=0v h iih5 ? 10 ? 10 a vdd=3.6v,vi=3.6v cmos output voltage l vol ? ? 0.05 v vdd=3.3v,|io|=1 a h voh 3.25 ? ? v cmos output current l iol 2 ? ? ma vdd=3.3v,vol=0.4v h ioh ? ? ? 2 ma vdd=3.3v,vol=2.6v output leakage current l iozl ? 10 ? 10 a vdd=3.6v,vo=0v h iozh ? 10 ? 10 a vdd=3.6v,vo=3.6v input pin capacitance ci ? 7 15 pf f=1mhz,vdd=0v output pin capacitance co ? 7 15 pf bi-directional pin capacitance cio ? 7 15 pf operating current 3.3v supply idd ? 140 ? ma M65665DSP rev.2.00, sep.04.2003, page 6 of 17 pin description pin no. name i/o function remarks 1 swm cmos output pip switch output 2 osd_sel cmos input output osd select 3 sdata cmos input/output (5v)*1 iic sda input/output 4 sclk cmos input (5v)*1 iic scl input 5 dvdd digital vdd vdd for digital part 6 dvss digital vss vss for digital part 7 bgps cmos output test output 8 sck cmos input test input connect to gnd 9 bgpm cmos output test output 10 fsc cmos input test input connect to gnd 11 test5 cmos input test input connect to gnd 12 testen cmos input test input connect to gnd 13 swmg cmos input pip switch output enable connect to vdd 14 reset cmos input power on reset input 15 csyncs cmos input sub picture external c-sync input 16 avdd(adc) analog vdd vdd for internal adc 17 vin(adc) analog sub picture v input of adc 18 uin(adc) analog sub picture u input of adc 19 vrb analog low level reference voltage output of adc 20 yin(adc) analog sub picture y input of adc 21 vrt analog high level reference voltage output of adc 22 cin(adc) analog sub picture c input of adc 23 avss(adc) analog vss vss for internal adc 24 cvbsin(adc) analog sub picture cvbs input of adc 25 avdd(vcxo) analog vdd vdd for vcxo 26 filter analog vcxo filter voltage connection 27 bias analog vcxo bias voltage connection 28 x'tal(ntsc) analog x'tal of ntsc connection 29 x'tal(pal-m) analog x'tal of pal-m connection 30 x'tal(pal-n) analog x'tal of pal-n connection 31 avss(vcxo) analog vss vss for vcxo 32 hd cmos input (5v)*1 main picture hd input 33 vd cmos input (5v)*1 main picture vd input 34 vdd(dac) analog vdd vdd for dac 35 osd_bin analog osd input of b 36 v(b)out analog sub picture v or b output 37 vz analog voltage reference output of dac 38 osd_gin analog osd input of g 39 u(b)out analog sub picture u or g output 40 avss(dac) analog vss vss for dac 41 osd_rin analog osd input of r 42 y(r)out analog sub picture y or r output note : 1. (5v) means 5v i/f tolerant M65665DSP rev.2.00, sep.04.2003, page 7 of 17 basic application example 1 when using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. x1 : siward 1-781-377-21(14.318180mhz ) 25 pip y(r) output i 2 c bus clock input i 2 c bus data input /output ana. ana. pip u(g) output pip v(b) output main vd input main hd input dig. pip sw output sub c(y/c) input 0.01u 0.01u 0.01u 0.47u 0.033u 0.22u 10u x1 10k 3.3 k 18 p 0 sub v input sub u input sub y(y/u/v) input sub cvbs and y(y/c) input 0.1u 0.1u 0.1u 0.1u osd selection input osd r input osd g input 0.01u osd b input 0.1u 0.1u 0.1u 3.3 m M65665DSP 31 22 23 24 26 27 28 29 30 41 32 33 34 35 36 37 38 39 40 42 18 12 21 20 19 17 16 15 14 13 2 11 10 9 8 7 6 5 4 3 1 ana. dig. dig. + 15 pin input when csync of sub picture is fed from external. 3.3v 0v 2 pin input level 3.3v 0v 3.3v 0v 1 pin output level 3.3v-5.0v 0v 32 pin /33 pin input leve l 0.7vpp (typ ) pedesta l 0.7vpp (typ ) pedestal 39 pin output level 36 pin output level 42 pin output level 0.7v (t yp) pedestal back ground white peak 0.66v(max) 1.0vpp (max ) pedestal whit e peak sync ti p 24 pin input level 22 pin input level 0.7vpp(typ ) pedesta l 0.7vpp (typ ) pedestal 18 pin input level 0.7vpp (typ ) pedestal 17 pin input level 20 pin input level 0.66v (max) 1.0vpp (max ) pedestal whit e peak sync ti p 0.01u 0.01u 0.01u M65665DSP rev.2.00, sep.04.2003, page 8 of 17 basic application example 2 when using any or all of the information contained in this diagrams, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. digital +3.3v power supply digital gnd analog +3.3v power supply analog gnd dig. ana. x1 : siward 1-781-377-21(14.318180mhz) x2 : siward 1-795-487-11(14.302444mhz) x3 : siward 1-795-486-11(14.328224mhz) M65665DSP rev.2.00, sep.04.2003, page 9 of 17 tv system block diagram y u y u yoke hd vd v v r g b deflection unit sw m composite video signal y/c separated video signal y c y c y c y/c separation y u v cv/y y/u/v component video sig nal M65665DSP pip signal processi ng video signal processi ng matr ix < y/u/v pip mixing system > r g yoke hd vd b r g b deflection unit swm composite video signal y/c separated video signal y c y c y c y/c separation y u v cv/y y/u/v component video sig nal m65665cfp/sp pip signal processi ng video signal processi ng osd_r osd_g osd_b osd_f.b. < r/g/b pip&osd mixing system > M65665DSP rev.2.00, sep.04.2003, page 10 of 17 i 2 c register information when using any or all of the information contained in this table, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. 1/9 ref. value address bit symbol read/ write reset value ntsc trinorma remarks 00h <7> disp w/r 0 1h 1h sub picture display : [0] off , [1] on <6> size_v w/r 0 0 0 sub picture vertical size : [0] 1/9 , [1] 1/16 <5> size_h w/r 0 0 0 sub picture horizontal size : [0] 1/9 , [1] 1/16 <4> wen w/r 0 1h 1h sub picture : [0] still , [1] moving <3> bgc w/r 0 0 0 back ground display : [0] off , [1] on <2> bgcs w/r 0 0 0 sub picture mute : [0] off , [1] on <1> free_run w/r 0 0 0 vcxo oscilation : [0] lock , [1] free run <0> xtalvlatch w/r 0 0 1h x'tal change v-latch enable : [0] disable , [1] enable 01h <7:0> vxa<7:0> w/r 0 20h 20h sub picture vertical position 02h <7:0> hxa<7:0> w/r 0 20h 20h sub picture horizontal position 03h <7> decode w/r 0 0 0 sub picture color decoder reset : [1] reset <6:0> contrast<6:0> w/r 0 32h 32h sub picture y or r dac output amplitude control 04h <7> killer w/r 0 0 0 sub picture color killer : [0] enable , [1] disable <6:0> u_dac<6:0> w/r 0 32h 32h sub picture u or g dac output amplitude control 05h <7> grc w/r 0 1h 1h frame display : [0] off , [1] on <6> yuvn_rgb_sel w/r 0 0 0 pip output mode selection : [0] yuv , [1] rgb <5:0> tint<5:0> w/r 0 0 0 sub picture tint control 06h <7:6> ext_sc_sel<1:0> w/r 0 1h 1h sub picture c-sync sep. selection : [0] int. digital , [1] int. auto slice , [2] ext.(18 pin) , [3] int. analog <5:4> dcont<1:0> w/r 0 0 0 sub picture int. c-sync sep. threshhold setting. <3:0> ht<3:0> w/r 0 ah ah sub picture display timing adjust 07h <7:6> input_sel<1:0> w/r 0 2h 2h sub picture input selection : [0] yc , [1] n.a. , [2] cvbs , [3] yuv <5:0> bg_start<5:0> w/r 0 0fh 0fh sub picture burst gate pulse position setting 08h <7:4> adj<3:0> w/r 0 4h 4h main/sub switch delay control <3:0> ydl<3:0> w/r 0 ah ah sub picture y/c delay adjust 09h <7:5> bgby<2:0> w/r 0 0 0 back ground u level setting <4:0> y_offset<4:0> w/r 0 0fh 0fh sub picture y bright control 0ah <7> vchip only w/r 0 1h 1h v-chip decode mode : [0] off , [1] on <6:4> bgry<2:0> w/r 0 0 0 back ground v level setting <3:0> bgy<3:0> w/r 0 6h 6h back ground y level setting 0bh <7:4> pedestv<3:0> w/r 0 0 0 sub picture v pedestal level (2's comp) <3:0> pedestu<3:0> w/r 0 0 0 sub picture u pedestal level (2's comp) M65665DSP rev.2.00, sep.04.2003, page 11 of 17 1/9 ref. value address bit symbol read/ write reset value ntsc trinorma remarks 0ch <7> uv_filter_off w/r 0 1h 1h sub picture u,v output filter [0] on , [1] off <6> set_acc w/r 0 0 1h address 0dh,0eh setting mode : [0] fixed value, [1] released to mcu <5:4> system_mode<1:0> w/r 0 0 3h system : [0]ntsc,[1]pal-m,[2]pal-n, [3]n.a. when auto_enable=0b [0]ntsc,[1]ntsc/pal-m,[2]ntsc/pal- n,[3]ntsc/pal-m/pal-n when auto enable=1h <3> set_size w/r 0 0 0 address 11h<6:0>,12h-14h setting mode : [0] fixed value, [1] released to mcu <2> set_vchip w/r 0 0 0 address 15h-17h setting mode : [0] fixed value, [1] released to mcu <1:0> sync_delay<1:0> w/r 0 0 0 sub picture sync. delay control 0dh <7:4> yuv_col<3:0> w/r 0 0 0 sub picture color control parameter when yuv input <3> c_gain_sel w/r 0 0 0 sub picture chroma : [0] x1 , [1] x2 <2> wdof_killer_on w/r 0 0 1h sub picture killer on when burst pll is unlock : [0] off , [1] on <1> set_yuv w/r 0 0 0 for test : 0 set only <0> cvf w/r 0 0 0 internal chroma comb filter : [0] on , [1] off 0eh <7> bitsel w/r 0 0 0 sub picture y clamp time constant : [0] x2 , [1] x1 <6> afcbitsel w/r 0 0 0 sub picture afc time constant : [0] x2 , [1] x1 <5:0> acc_level<5:0> w/r 0 15h 15h sub picture color decoder amplitude 0fh <7> auto_enable w/r 0 0 1h system automatic judgment : [0] off , [1] on <6> v50posien w/r 0 0 0 pip v-position mode : [0] vxa , [1] (vxa)x1.2 when vd is 50hz <5> paln_disable w/r 0 0 0 main picture pal-n : [0] enable , [1] disable <4> inv_rff w/r 0 0 0 invert main picture field definition : [0] normal , [1] invert <3> inv_wff w/r 0 0 0 invert sub picture field definition : [0] normal , [1] invert <2> vmode w/r 0 0 1h vertical display mode when pal-n input : [0] normal , [1] wide <1> rff_fix w/r 0 0 0 main picture field fix : [0] not fix , [1] fix <0> auto_rff_fix w/r 0 1h 0 automatic 50/60hz judgment : [0] enable , [1] disable M65665DSP rev.2.00, sep.04.2003, page 12 of 17 1/9 ref. value address bit symbol read/ write reset value ntsc trinorma remarks 10h <7:6> no_bst_lvl<1:0> w/r 0 0 0 for test <5:4> bw_det_lvl<1:0> w/r 0 0 1h bw det. threshold setting : [0] off , [1] 16mv , [2] 32mv , [3] 64mv <3:0> palry<3:0> w/r 0 0 1h threshold control of ident judgment of sub picture decoder 11h <7> fvjdgsel w/r 0 0 0 vertical frequency judging mode [0]:based on 5 field, [1]:based on 4 field. <6:0> hya<6:0> w/r 0 37h 37h sub picture horizontal display pixel 12h <7:0> vya<7:0> w/r 0 44h 44h sub picture vertical display line number 13h <7:2> hx<5:0> w/r 0 1eh 1eh sub picture horizontal capture position (coarse) <1:0> hp<1:0> w/r 0 0 0 sub picture horizontal capture position (fine) 14h <7:6> mvc<1:0> w/r 0 0 0 sub picture c-sync input mask period : [0] 48usec , [1] 44usec , [2] 53usec , [3] off <5:0> vxs<5:0> w/r 0 29h 29h sub picture sample start line 15h <7> ? w/r 0 0 0 for test : 0 set only <6> plus w/r 0 0 0 for test : 0 set only <5> ? w/r 0 0 0 for test : 0 set only <4:0> line_num<4:0> w/r 0 11h 11h data slicer line selection 16h <7:0> stb_dly<7:0> w/r 0 40h 40h data slicer start bit detection parameter 17h <7:0> l_level<7:0> w/r 0 82h 82h data slicer data slice parameter 18h <7> edge_on w/r 0 1h 1h frame data independent control : [0] disable , [1] enable <6:4> bgby_edge<2:0> w/r 0 0 0 frame data independent b-y data setting <3:0> bgy_edge<3:0> w/r 0 ch ch frame data independent y data setting 19h <7:5> bgry_edge<2:0> w/r 0 0 0 frame data independent r-y data setting <4> hpfoff w/r 0 0 0 sub picture y output hpf : [0] on , [1] off <3:0> free_run_adj<3:0> w/r 0 0 2h frequency adjustment control when free run mode (2's comp) 1ah <7:0> sub_palm_judge <7:0> w/r 0 0 26h parameter setting for pal-m/ntsc judgment 1bh <7:6> export<1:0> w/r 0 0 0 ext. port (7 pin) : [0] "0" output , [1] "1" output , [2 or 3] sub bgp <5> inv_uv w/r 0 0 0 invert u,v output value : [0] normal , [1] invert <4> afc_off w/r 0 0 0 sub picture afc : [0] on , [1] off <3:0> hadj<3:0> w/r 0 0 0 parameter setting for pal-m/ntsc judgment 1ch <7> pinoe w/r 0 0 0 for test <6:0> v_dac<6:0> w/r 0 32h 32h sub picture v or b dac output amplitude control 1dh <7:0> pinoe<7:0> w/r 0 e6h e6h for test 1eh <7:0> ? w/r 0 0 0 for test M65665DSP rev.2.00, sep.04.2003, page 13 of 17 1/9 ref. value address bit symbol read/ write reset value ntsc trinorma remarks 1fh <7:6> system_state<1:0> r color state : [0] ntsc , [1] pal-m , [2] pal-n , [3] n.a. (read only) <5> main_paln r main is : [0] not pal-n , [1] pal-n (read only) <4> sub_unlock r vcxo is : [0] lock , [1] unlock (read only) <3> sub_paln r sub is : [0] not pal-n , [1] pal-n (read only) <2> rdof r main picture v sync is [0] present , [1] not present (read only) <1> sub_bw r sub picture burst is : [0] not present , [1] present (read only) <0> wdof r sub picture v sync is [0] present , [1] not present (read only) 20h <7> killerstatus r sub picture killer status : [0] not active , [1] active (read only) <6> ? r test use (read only) <5> wdof r sub picture v sync is [0] present , [1] not present (read only) <4> eds_ack2 r eds data flag of even field : [0] no eds , [1] eds (read only) <3> eds_ack1 r eds data flag of odd field : [0] no eds , [1] eds (read only) <2> signal_ok r test use (read only) <1> read_reqb r read request of even field : [0] no , [1] requesting (read only) <0> read_reqa r read request of odd field : [0] no , [1] requesting (read only) 21h <7:0> pdb<15:8> r even field sliced data upper 8bit (read only) 22h <7:0> pdb<7:0> r even field sliced data lower 8bit (read only) 23h <7:0> pda<15:8> r odd field sliced data upper 8bit (read only) 24h <7:0> pda<7:0> r odd field sliced data lower 8bit (read only) M65665DSP rev.2.00, sep.04.2003, page 14 of 17 the relation of input signal 32-pin (main-hd) and 33-pin (main-vd) is shown below 32-pin input (main-hd) 33-pin input (main-vd) [even to odd] +10 se c -10usec +21.75 sec +41.75 sec 33-pin input (main-vd) [odd to even] 0 +53.5 se c 31.75 s 4h 1h end of vertical equalization pulse vd input prohibition time of changing 33-pin signa l 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s 20 s vd in put driving method and operating specification for serial interface data (1) serial data transmission completion and start a low-to-high transition of the data (serial data) line while the clk (serial clock) is high, that completes the serial transmission and makes the bus free. a high-to-low transition of the data line while the clk is high, that starts the serial transmission and waits for the following clk and data inputs. (2) serial data transmission the data are transmitted in the most significant bit (msb) first by one-byte unit on the data line successively. one- byte data transmission is completed by 9 clock cycles, the former 8 cycles are for address/data and the latter one is for acknowledge detection. (in writing state, sdata outputs ? l' under these two conditions ; 1) the coincidence of two address data for the address data transmission, 2) the completion of 8-bit setting data transfer. in reading state, sdata outputs ? l' with the address coincidence and sdata becomes high-impedance for detecting acknowledge input from the master (micro processor) after sending 8-bit setting data.) for address/data transmission, data must change while clk is 'l'. (the data change while clk is 'h' or the simultaneous change of clk and data, that will be a false operation because of undistinguished condition from the completion / start of serial data transfer). after the beginning of serial data transmission, the total number of data bytes that can be transferred are not limited. (3) the byte format of data transmission (the sequence of data transmission) a. the byte format during data writing to M65665DSP are shown as follows. in right after the forming of serial data transmitting state, the slave address 24h (00100100b) is transferred. afterwards, the internal register address (1 byte) and writing data (by 1 byte unit) are transferred successively. several bytes of M65665DSP rev.2.00, sep.04.2003, page 15 of 17 writing data can be handled in the one transmission. in this operation, the setting data are written into the address register whose address is increased one in initially transferred internal register address. b. the byte format during data reading from M65665DSP are shown as follows. before data reading from M65665DSP, whose internal address need to be set by the data reading/transmitting. after the data reading/transmitting, the operation of "serial data transmission completion and start" (described in (1)) is necessary. continuously, the slave address 25h (00100101b) is sent, and then the read out data are available on sdata as ?l?/?high-impedance? pattern. several bytes of reading data can be handled in the one transmission, too. in this operation, the setting data also are written into the address register whose address is increased one in initially transferred internal register address. the examples of serial byte transmission format (1) the writing operation of the setting data (aah) into M65665DSP internal address of 00h s : operation of serial transmission start a : acknowledge detection e : operation of serial transmission completi on s24 h a00 h a aah a e confirmation of bus free (data='h ') transmission ac tivation (2) the writing operation of the setting data (ffh, 80h, eeh) into M65665DSP internal address of 04h to 06h confirmation of bus free (data='h ') transmission ac tivation s24 h a04 h aff h a e 80 h a eeh a (3) the reading operation of the setting data from M65665DSP internal address of 00h a' : bus free operation by the master (micro processor ) confirmation of bus free (data='h ') transmission ac tivation s24 h a00 h a25 h a$$ h a' es M65665DSP rev.2.00, sep.04.2003, page 16 of 17 (4) the reading operation of the setting data from M65665DSP internal address of 04h to 06h. a" : output 'l' operation by the master (micro processor) confirmation of bus free (data='h ') transmission ac tivation s24 h a04 h a25 h a$$ h a" e s$$ h a" $$ h a' timing diagram 1 23 45 6 789 1 sclk (4 pin) sdata (3 pin ) bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) ack detec. bit7 (msb) sdata (3 pin) (r ead data) bit7 (msb) bit6 bit5 bit4 bit3 bit2 bit1 bit0 (lsb) bit7 (msb ) M65665DSP rev.2.00, sep.04.2003, page 17 of 17 package dimensions sdip42-p-600-1.78 weight(g) ? jedec code 4.1 eiaj package code lead material alloy 42/cu alloy 42p4b plastic 42pin 600mil sdip symbol min nom max a a 2 b b 1 b 2 c e d l dimension in millimeters a 1 0.51 ? ? ? 3.8 ? 0.35 0.45 0.55 0.9 1.0 1.3 0.63 0.73 1.03 0.22 0.27 0.34 36.5 36.7 36.9 12.85 13.0 13.15 ? 1.778 ? ? 15.24 ? 3.0 ? ? 0? ? 15? ? ? 5.5 e e 1 42 22 21 1 e c e 1 a 2 a 1 b b 1 b 2 e l a seating plane d mmp ? 2003. renesas technolo gy corp., all ri g hts reserved. printed in japan . colo p hon 1.0 keep safet y first in y our circuit desi g ns ! 1. renesas technolo gy corp. puts the maximum effort into makin g semiconductor products better and more reliable, but there is alwa y s the possibilit y that trouble m a y occur with them. trouble with semiconductors ma y lead to personal in j ur y , fire or propert y dama g e . remember to give due consideration to safety when making your circuit designs, with appropriate measures such as (i) placem ent of substitutive, auxiliary circuits, (ii) use of nonflammable material or (iii) prevention against any malfunction or mishap. notes regarding these materials 1. these materials are intended as a reference to assist our customers in the selection of the renesas technology corp. product best suited to the customer's application; they do not convey any license under any intellectual property rights, or any other rights, belonging to renesas t echnology corp. or a third party. 2. renesas technology corp. assumes no responsibility for any damage, or infringement of any third-party's rights, originating in the use of any product data, diagrams, charts, programs, algorithms, or circuit application examples contained in these materials. 3. all information contained in these materials, including product data, diagrams, charts, programs and algorithms represents i nformation on products at the time of publication of these materials, and are subject to change by renesas technology corp. without notice due to product improvement s or other reasons. it is therefore recommended that customers contact renesas technology corp. or an authorized renesas technology corp. product distrib utor for the latest product information before purchasing a product listed herein. the information described here may contain technical inaccuracies or typographical errors. renesas technology corp. assumes no responsibility for any damage, liability, or other loss rising from these inaccuracies or errors. please also pay attention to information published by renesas technology corp. by various means, including the renesas tech nology corp. semiconductor home page (http://www.renesas.com). 4. when using any or all of the information contained in these materials, including product data, diagrams, charts, programs, a nd algorithms, please be sure to evaluate all information as a total system before making a final decision on the applicability of the information and products. renesas technology corp. assumes no responsibility for any damage, liability or other loss resulting from the information contained herein. 5. renesas technology corp. semiconductors are not designed or manufactured for use in a device or system that is used under ci rcumstances in which human life is potentially at stake. please contact renesas technology corp. or an authorized renesas technology corp. product distributor when considering the use of a product contained herein for any specific purposes, such as apparatus or systems for transportation, vehicular, medical, aerosp ace, nuclear, or undersea repeater use. 6. the prior written approval of renesas technolo gy corp. is necessar y to reprint or reproduce in whole or in part these materials . 7 . if these products or technolo g ies are sub j ect to the japanese export control restrictions, the y must be exported under a license from the japanese g overnment and cannot b e imported into a countr y other than the approved destination. an y diversion or reexport contrar y to the export control laws and re g ulatio n s of japan and/or the countr y of destination is prohibited . 8. please contact renesas technolo gy corp. for further details on these materials or the products contained therein . s ales strate g ic plannin g div. nippon bld g ., 2-6-2, ohte-machi, chi y oda-ku, tok y o 100-0004, japa n htt p ://www.renesas.co m renesas technology america, inc. 450 holger way, san jose, ca 95134-1368, u.s.a tel: <1> (408) 382-7500 fax: <1> (408) 382-7501 renesas technology europe limited. dukes meadow, millboard road, bourne end, buckinghamshire, sl8 5fh, united kingdom tel: <44> (1628) 585 100, fax: <44> (1628) 585 900 renesas technology europe gmbh dornacher str. 3, d-85622 feldkirchen, germany tel: <49> (89) 380 70 0, fax: <49> (89) 929 30 11 renesas technology hong kong ltd. 7/f., north tower, world finance centre, harbour city, canton road, hong kong tel: <852> 2265-6688, fax: <852> 2375-6836 renesas technology taiwan co., ltd. fl 10, #99, fu-hsing n. rd., taipei, taiwan tel: <886> (2) 2715-2888, fax: <886> (2) 2713-2999 renesas technology (shanghai) co., ltd. 26/f., ruijin building, no.205 maoming road (s), shanghai 200020, china tel: <86> (21) 6472-1001, fax: <86> (21) 6415-2952 renesas technology singapore pte. ltd. 1, harbour front avenue, #06-10, keppel bay tower, singapore 098632 tel: <65> 6213-0200, fax: <65> 6278-8001 renesas sales offices |
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